Research And Design Of Low-Voltage Low-Power CMOS Transceiver RF Front-End Circuits

In the last few years, the rapid development of the RF and wireless communication applications has been widely used in each field of the society. Different communication standards, such as wireless local area networks (WLAN), Bluetooth, ultra-wideband (UWB) communication, wideband multi-standard communications with2G/3G/B3G protocol, are playing important roles in specific wireless communication fields. The growing demand of the RF and wireless communication applications has attracted a great deal of researches on designing high performance RF and wireless communication devices, which can be used in any place and any time. Accordingly, the RF and wireless communication devices are required to be lower voltage, lower power, smaller size and higher performance.With the rapid development of wireless communication applications, the design of transceiver RF front-end has brought great challenges. The transceiver RF front-end is the interface circuit between the antenna and the digital baseband processor. It requires to amplify the received weak signal from the antenna in the GHz band, while transmit the high power signal to the antenna in the same frequency band. The transceiver RF front-end need to complete the following operations:the received weak RF signal from the antenna is amplified and down-converted to a baseband signal in the receiver path; the baseband signal from the baseband processor is up-converted to a RF signal and amplified to emission in the transmitter path. In the transceiver RF front-end, low noise amplifier (LNA), down-conversion mixer, up-conversion mixer and driver amplifier are essential building blocks. To realize the low voltage, low power, high integration and high performance of the transceiver RF front end, it has become a bottleneck in the GHz band. This dissertation has proposed the design and research of CMOS transceiver RF front-end, which can satisfy the requirements of low voltage, low power, high integration and high performance. The main innovative work of this dissertation is as follows.(1) This dissertation presents a low complexity UWB3.1-10.6GHz LNA using a Chartered0.18μm CMOS technology. The UWB LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the-3dB bandwidth of the overall amplifier simultaneously. The implemented UWB LNA presents a maximum power gain of15.6dB, a high reverse isolation of-45dB and good input/output return losses are better than-lOdB in the frequency range of3.1-10.6GHz. An excellent noise figure (NF) of2.8-4.7dB was obtained in the required band with a power dissipation of8.1mW under a supply voltage of1.5V. An input-referred third-order intercept point (IIP3) is-7.1dBm at6GHz. The chip area including testing pads is only0.8mmx0.9mm. The results have shown that the proposed LNA is suitable for the UWB system applications, while meets the requirement of low voltage and low power operations.(2) This dissertation presents a0.5-4.0GHz wideband current-mode down-conversion mixer using a TSMC0.18μm CMOS technology. By using the current-mode approach, the current mirror amplifier and passive switching core are merged seamlessly into a single mixer component. The current mirror amplifier is used to implement the input and output stages of the mixer, and a passive switching core is embedded between the gates of the input and output transistors of the current mirror to achieve mixing function. The proposed mixer does not use the inductor and resistor of passive elements, but it can combine the advantages of active and passive mixers simultaneously. Over the entire bandwidth, the mixer features a measured power conversion gain of8.9-9.6dB, a double-sideband NF of6.9-9.3dB, an IIP3of2.0-5.8dBm, while consuming9.6mW from a1.2V supply voltage. The mixer occupies the active area of0.43mm×0.46mm including testing pads. The results have shown that the proposed down-conversion mixer is suitable for the wideband multi-standard system applications, while meets the requirement of low voltage and low power operations.(3) This dissertation presents a2.4GHz current-mode transmitter RF front-end using a Chartered0.18μm CMOS technology. The transmitter RF front-end is integrated with a current-mode up-conversion mixer as well as a transimpedance driver amplifier, which could eliminate an unnecessary current-to-voltage (I-V) and voltage-to-current (V-I) conversions. The up-conversion mixer uses the input current-squaring circuit of cross-coupled topology as the input stage, which can significantly improve the linearity and consume a small amount of DC current. Two stage transimpedance driver amplifier shares the inter-stage capacitive cross-coupling technique which provides high power gain as well as low power consumption. The measured results show that at2.4GHz, the transmitter RF front-end provides15.5dB of power conversion gain, the output P-1dB of3dBm, the output-referred third-order intercept point (OIP3) of13.8dBm, the maximum output power of4.5dBm, while drawing only7.2mW under a supply voltage of1.2V. The chip area including testing pads is only0.9mm×1.1mm. The results have shown that the proposed transmitter RF front-end is suitable for Bluetooth and IEEE802.11b WLAN system applications, while meets the requirement of low voltage and low power operations.(4) This dissertation presents a2.4GHz improved Gilbert up-conversion mixer using a Chartered0.18μm CMOS technology. In the proposed mixer, the double balanced Gilbert cell topology was adopted and several improved techniques were used. The proposed mixer uses a resistive current-reuse and capacitive cross-coupling techniques in the driver stage, which can significantly improve the conversion gain and linearity and consume a small amount of current. The proposed mixer uses a current-bleeding technique in the switching stage, which can enhance the conversion gain as well as improve switch efficiency. The post-layout simulation results demonstrate that at2.4GHz, the circuit provides7.1dB of conversion gain, the IIP3of11.3dBm, the double-sideband NF of12.7dB, while drawing only6mW under a supply voltage of1.2V. The chip area including testing pads is only0.65mmx0.75mm. The results have shown that the proposed up-conversion mixer is suitable for Bluetooth and IEEE802.11b WLAN system applications, while meets the requirement of low voltage and low power operations.