Research And Design Of A Output-Capacitor CMOS LDO With Low Power And High Stability

With the prevalence and popularity of portable electronic devices, the integrated circuit So C which requires more features can be completely integrated on-chip is also growing up. Power management chip is absolutely included. As the essential building block of power management chips, the conventional low-dropout linear regulators LDO needs a large off-chip capacitor for the purpose of loop stability at the output. However, the stability of the output-capacitorless LDO system is facing great challenges, including frequency response and transient response. The power consumption of LDO need to further reduce adhering to the basic principles of the development of energy conservation as well as improving the battery life and standby time of electronic devices, therefore, the low power and high stability output-capacitorless LDO turns into the development trend.The feedback of the conventional output-capacitorless LDO is based on sampling resistor network which needs large area, and that demands more for the error amplifier. This paper adopts a new feedback form that is the FVF structure, which means the flipped voltage follower.In fact, the essence of the idea is feedback controlled a single transistor. With this structure, not only the LDO circuit can be easier, but also the difficulty of amplifier design is reduced. In this paper, the basic structure based LDO FVF is improved with better performance including the followings: good regulation with adding an amplifier, frequency compensation with miller compensation and better transient response with dynamic bias circuit. Finally, The design of the low-power and high stability output-capacitorless CMOS LDO is completed, which can be applied in digital modules’ power supply of the So C system.The design is based on the 40 nm CMOS process, which completes the circuit simulation and layout design. The followings are obtained: the input voltage range is from 1.5 V to 3.3 V,the normal input voltage is 1.8 V, the output voltage is 1.2 V, the load current range is from 1 m A to 50 m A, the minimum dropout voltage is 293 m V; the load regulation is 0.173 ppm, the linear regulation is 0.134%, the PSRR at low frequency is 60.4 d B, the overshoot voltage of transient response for 91.24 m V, the longest response time is 4.37 μs; the power consumption of the LDO core circuit is only 16 μA, the phase margin of the feedback loop is as low as 80° in all range of load current, the required capacitor is about 40 p F which can be fully integrated on the chip; the layout area used is about 384 μm × 314 μm. In summary, the design meets the application requirements with those characteristics including low power consumption, high stability and on-chip capacitor.