Research And Design Of Low Power Output-Capacitor-Less LDO With High Stability

Low dropout(LDO)linear regulators are functional blocks in power management IC that are easy to implement and have low noise levels and are widely used in many portable electronic devices,especially for high performance circuits and noise sensitive applications.In the current SOC on-chip system,a large number of functional circuits are integrated,including logic control units,memory units,analog amplifier circuits,power management modules,and the like.These functional circuits require increasingly higher performance requirements for regulated sources such as high stability,low power consumption,and low noise.In order to achieve such high performance,traditional low-dropout linear regulators usually use large-capacity compensation at the load end,but the current on-chip SOC system is developing in a smaller and smaller chip area,but the transistor integration is getting higher and higher.However,the large capacitance It needs to occupy a large area of the substrate or chip to achieve,which is in contradiction with the improvement of integration.At present,there are some circuit design methods to solve this contradiction.Output-capacitor-less LDO is one of the best solutions.Many scholars and engineers have published a large number of documents and circuit examples,but there are still some problems that have not been solved,such as With low dropout,low quiescent current,small transient undershoot/overshoot and high stability,and the like.However,these performances are difficult to achieve at the same time.In the current face of these problems,this paper has done the following work:This paper designs an output-capacitor-less LDO based on 55 nm CMOS process with low power consumption and high stability,which is applied to the on-chip SOC circuit to meet the requirements of high stability,low power consumption and low noise.(1)By adopting adaptive power tube technology,the corresponding power transistors are switched between the two-pole and three-stage cascaded topology according to the condition of the load current;the low power-to-length ratio auxiliary power tube is used at low load current,high load current The main power tube is used to save power and improve current utilization efficiency.(2)By using a dynamic bias network,the dynamic bias network transistor is proportional to the secondary power tube,and the current of theerror amplifier is increased as the current of the secondary power tube increases,thereby increasing the bandwidth and improving the load transient.Responsive performance.(3)The circuit is reduced by overshoot so that the output overshoot voltage of the LDO is reduced under load transient conditions.(4)The stability of the entire system is achieved by using the cascode Miller compensation technique.The simulation results show that the input voltage range of this LDO is 1.1V-1.4V,which can achieve a stable output voltage of 1V.In the case of zero load current,the LDO consumes 4.8?A.When the input voltage is 1.4V,the output voltage is 1V,and the load is 100mA/0.3?s,the transient response time is less than 3.7?s;the load transient response overshoot and undershoot voltage are less than 146 mV.In addition,the load regulation rate at full load is 3.09 ?V/m A,and the low-frequency power supply rejection ratio is-66.58 dB.