| In recent years, the development of the radar technology tends to miniaturization, low power consumption, multifunction and high accuracy, so the constrains to the radar signal processing system has gradually become strict. The traditional single pulse digital signal processing chip cannot meet the technical requirements of the modern radar, especially the single pulse radar and synthetic aperture radar.Traditional signal processing system design usually does not consider the system's scalability and versatility, except for a specific algorithm implementation or use. Therefore, both the distribution of resources and the interconnection between boards are of specificity, but also with some limitations. The whole system needs to be redesigned when the requirement of processing result, the amount of data processed or the object of the processing object is changed. The system designed in this paper is based on the performance index of the system, and the scalability and generality of the system are considered. The signal processing board is ba sed on FPGA+ multi core DSP architecture, and the interface is connected with the external system through the standard bus interface, so as to realize the real-time processing of radar signal.DSP plays an important role in radar signal processing. In the application of array antenna in radar, a signal processing system is required to have a higher data bandwidth and a higher computational performance. The main methods to improve the performance of the single core processor include improving the storage performance, using parallel operation instruction, and increasing the clock frequency, but these methods also limit the performance of the single core processor. AD TS201 is a kind of popular DSP chip currently used in radar signal processing, however its performance has been unable to meet the needs of the development of high integration, high bandwidth and high computing radar real-time signal processing platform.In summary, this paper has a certain practical value and research significance. The development of future signal processing will be based on the network topology, but TS201 does not have the high-speed interface like Rapid IO, PCIe, etc. TI launched the multi core DSP- TMS320C6678, which uses Key Stone architecture, has the advantages of high integration, low power consumption, strong computing ability, etc. At the same time, the high speed serial interface is integrated in the chip. Therefore, this DSP chip can meet the needs of the development of modern radar signal processing platform.With the development of multi-core processor, new challenges emerge. The full exploit of the performance of multi-core processors dose not only rely on the support of the software architecture, but also the improvement of hardware structure. The new problems occurr ed in the application development of multi-core processors are: multi core communication, task load balancing, storage structure design.In view of the above problems, this paper mainly does the following five aspects of work: First, according to requirement of an actual project, design of signal processing platform with universal and scalable, and gives the specific implementation process of the signal processing algorithm. Second, the basic working principle of high speed interface SRIO, PCIe, and the specific implementation of the system are studied. Third, a detailed introduction to the TMS320C6678 used for hardware signal to achieve synchronization method, multi task allocation, and cache performance optimization technology. Fourth, combining with the practical application, the method of SPI is designed. Fifth, a comprehensive analysis of the specific needs of the system to achieve the pulse Doppler mode and synthetic aperture imaging mode, detailed consideration of the task allocation, multi kernel synchronization, memory allocation, and other aspects of the factors, and a specific pattern of switching implementation scheme is given. |
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