The Design Of Scrambler And Descrambler Circuit In USB3.0 Based On FPGA

USB2.0 (universal serial bus 2.0) interface is widely used in connecting the computer with peripheral device. With the increasing of data files transmitted, the existing transmission rate of USB2.0 has been unable to meet the bandwidth requirements of massive data file transfered. In 2008, Intel, Microsoft, NEC and other companies jointly introduced a new generation of USB standard-USB3.0, its transmission rate is ten times as much as the USB2.0, the maximum transmission bandwidth is up to 5Gbps. USB3.0 is perfectly compatible with USB2.0, and is more efficient and less power efficient than USB2.0. Now more and more computers and electronic devices are equipped with USB3.0 interface.The main content of this paper is to use FPGA to design the scrambler and descrambler circuit in the USB3.0 physical layer. At first, the paper introduces the research background and the research status of scrambler and descrambler circuit, and then analyzes the architecture of USB3.0 and he main function modules of physical layer. Since the paper uses FPGA to design the circuit of the scrambler, the related content of FPGA were introduced, mainly including the structure of FPGA and circuit design process in FPGA.According to the design requirements of scrambler and descrambler circuit in the physical layer of the USB2.0,the paper,Combined with FPGA characteristics and design principles, designes a parallel scrambler circuit and descramble circuit using Verilog in RTL level, and validate the function simulation of the design. Finally, the circuit will be downloaded to FPGA chip for debugging results using logic analyzer-SignalTap embedded in FPGA, verifying whether the results meet the design expectations in real time.