USB3.0Link Layer Design And Verification

USB3.0has10times faster than current data transmission products. It uses the same architecture as existing USB with backward compatibility to USB standards, supports optical fiber transmission in the future, and has the usability of plug and play as traditional USB technology.The dissertation focuses on USB3.0link layer design. It can be mainly divided into the theory part and design part on the structure.In the theory part, the dissertation starts from USB3.0standard protocol, introduces the basic structure of USB3.0, the function of each parts, communication mechanism, information packets, data transmission mode and so on according to our understand and analysis, and analyzes the lmowledge of USB3.0link layer including the packets definition of data link layer, error tests, and principle and processing of sending and receiving data packets.In the design design, the dissertation does structure design and module partitioning for the USB3.0link layer, which is divided into in four modules:the receiver, transmitter, states control&error detection, and power management, and design each module separately in RTL-level using Verilog hardware description language, then builds the verification platform, uses comprehensive simulation tools to verify the four modules and the whole RTL design of USB3.0link layer consisting of those four modules, and downloads it to FPGA in the hardware for debugging, verification and performance analysis. Functional simulation and FPGA verification results show that our design are fairly satisfactory.