Research And Design Of USB3.0 Data Scrambling And Descrambling Circuit Based On FPGA

USB3.0 is an interface specification launched by Intel and Microsoft, which is based on USB2.0 and further developed the USB technology. The maximum transmission bandwidth of USB2.0 is 480Mbps, while the maximum transmission bandwidth of USB3.0 is 5Gbps, so that USB3.0 is more suitable than USB2.0 in transmitting massive data. USB3.0 is more efficient and less power efficient than USB2.0, and specially strengthen the power management function. USB3.0 is compatible with USB2.0, and it also facilitates the upgrading of products using USB2.0 interface. USB3.0 interface will be widely used in electronic products in the future.This thesis has mainly designed the data scrambling and descrambling circuit of USB3.0 physical layer according to the requirements of the design agreement. USB3.0 physical layer can be divided into digital circuit part and analog circuit part. The digital circuit part consists of data scrambling and descrambling,8b / 10b codec, K28.5 detection module, elastic buffer module, serial and parallel conversion circuit. The data scrambling and descrambling circuit plays an important role in USB3.0 physical layer,and closely related to the 8b / 10b codec module. So it is necessary to research and design the 8b / 10b codec module.After putting forward a parallel way to achieve the circuits on the basis of the analysis about the principles and rules of the data scrambling and data descrambling .This thesis used the FPGA to verify logic function, and used Verilog hardware language to describe the circuit, then used Modelsim to simulate function. Results shows that the designed circuit can meet the equipment of USB3.0 data communication protocol.