Stress tests of analog CMOS ICs for gate-oxide reliability enhancement

Yield and reliability are two factors affecting the profitability of semiconductor manufacturing. In the manufacturing process of modern VLSI semiconductor devices, gate-oxide defects have been found as one of the major causes for the reliability problems of CMOS integrated circuits (ICs). Stress testing is a technique used to weed-out early life failures by applying higher than usual levels of stress to speed up the deterioration of electronic devices. The industry standard methods for stress testing have been high-temperature burn-in and high-voltage stress. Burn-in decreases failure rate of a product during the early field life, but overall cost and turn around time are of concerns. The added manufacturing cost may range from 5% to 40% of the total product cost, depending on the burn-in time, qualities of ICs, and product complexity. Extreme-voltage stress test aims at enhancing both quality and reliability without performing the high-cost burn-in test process. Extreme-voltage screening has been successfully implemented to enhance gate-oxide reliability of digital CMOS ICs. However, the success has not yet been extended to its analog counterparts. Today, almost all IC manufacturers employ the digital circuits extreme-voltage screening process for the analog modules in mixed-signal CMOS ICs. This study initiates the research on extreme-voltage stress of analog CMOS ICs with the goal to improve their quality and reliability cost effectively.; This study presents an efficient yet effective extreme-voltage stress test process for analog CMOS circuits analytically. It develops the framework of an automatic stress test system for analog circuits, that integrates three major components—Stress Vector Generator, Stressability Analyzer , and Stressability Design Methodology.; Stress vector generator and stressability analyzer are analysis tools used by the stress test process to determine the stressability of a given circuit. Stress vector generator can provide optimal set of stress vectors and stressability analyzer determines the stressability of the circuit based on the selected stress vectors. Stressability design methodology of the stress test process is employed during design phase to ensure desired stressability of the circuit. This design methodology utilizes the two analysis tools and stressability enhancement process to meet stressability requirements during the design phase.; This work defines the fundamental concepts required for proper stressability of analog circuits. Based on these concepts it develops stress vector generation procedure for extreme-voltage stress test and burn-in of analog CMOS ICs. It also presents stressability analysis process that can locate portions of a circuit having poor stressability. It then describes an effective stressability enhancement process to improve the stressability of problem areas identified by the stressability analysis. The development is readily applicable to digital and mixed signal CMOS ICs. For large circuits, it presents a circuit decomposition model so that the developed processes can be applied in a hierarchical manner. This study also analyzes the stressability of various gate-oxide reliability enhancement techniques currently employed in the industry. It compares the existing methods and identifies the trade-offs that will determine the selection of proper stress test.