| esting in the semiconductor industry is conducted on specially designed test chips that are essential for the rapid diagnosis of failure, improvement of yield, and thus the timely introduction of products to the market. Although test chips are pervasive during semiconductor technology development, there has been very little work in the area of computer-aided design tools for testing.;This thesis describes a new, computer-aided design tool based on widely used, commercially available tools that dramatically improves the productivity of testing related tasks. The environment is based on TMA's TSUPREM4, Cadence's OPUS, and HP's IC-MS and can be used for the selection of test structures, rapid generation of test chips, and automatic compilation of a vast majority of the parametric test software needed for electrical testing.;The test structure advisor, the first component of the environment, uses cross-sections of the technology being developed to systematically select test structures. Using structural decomposition, the advisor identifies regions of potential failure and, extracting information from the product chip, recommends test structures that can be used in the characterization and debugging of the technology.;The second component of the environment, the parameterized test structure libraries, is used with the list of recommended test structures for the rapid generation of test chips. All the test structures in these libraries are parameterized according to their physical dimensions and mask level description, thus can be customized and used in different test chips.;Finally, the layout editor is coupled with the test shell enabling the sharing of information across the environments. Therefore, parameters can be extracted from the layout editor and automatically formatted and compiled into test software that is compatible with the IC-MS test shell.;This environment has been used in the design of several test chips for Stanford research projects. Overall, this environment produces a... |
