The Design Of OTP Memory Readout System Basing On MTM Antifuse

The rapid development of information technology puts forward higher requirements for information security in information transmission. Memory is the main carrier of data storage and information exchange in information technology, and thus becomes a top priority of the semiconductor industry. Under such a circumstance, as a non-volatile memory which can only be programmed once, OTP memory, by its virtue of extreme reliability and immunity against radiation,has been widely used in security features demanding fields, for example: aerospace, defense, international space station, and so on.The purpose of the thesis is designing the OTP memory reading system basing on MTM antifuse, comprised by the following sub-modules: address detection, pulse stretching, the control signal generator, the sense amplifier, DICE latch, a bi-directional data ports and so on. This thesis provides an overview of the overall structure of OTP memory, designs the storage bits basing on antifuse, and analyzes how it works. Then makes a full theoretical study of OTP memory readout system, including which kind of circuit configuration to use for the various sub-circuit blocks, the influences on the performance indicators by the parasitic factors and so on. Especially makes a detailed in-depth study for the sensitive amplifiers,including the effect of the bit line load on the read time of the memory and the effects of parasitic capacitance on the read threshold. Basing on the theoretical analysis,the thesis designs the readout circuit basing on the MTM antifuse. A large number of simulations among the overall design process quantifies the effect of the parasitic parameters on the performance indicators under each case comprised by different process corner and temperature,for example,the read time and the read threshold is 25.5ns and 9.8KΩ. After the design and verification of the layout we extract the parasitic parameters of the circuit, the results of the post-simulation by FineSim show the key performance indicators are designed to meet the project requirements. Finally, we make a suitable chip test program for this design basing on previous experience to improve the efficiency of the chip test after the tapeout completed.Readout circuit designed in this thesis by using a two-stage DICE latches with the ability of anti-interference has higher reliability, which can ensure the correct reading of programmed information in the memory bit. Meanwhile, the readout circuit has good portability, only minor changes will make the readout circuit applicable to OTP memory of different capacities and different anti-fuse types.