Study On Quasi-cyclic LDPC Codes And Its FPGA Implementation

Low-Density Parity-Check(LDPC) codes have been shown to have good error correcting performance that approaches the Shannon limit. Due to the advantages of LDPC codes, such as lower complexity of decoding and lower error floor, their applications have received great interests and have become one of most attractive field in channel coding community. Quasi-cyclic LDPC codes form an important subclass of LDPC codes. These codes have advantages in many respects over other types of LDPC codes, such as construction of codes, encoding and decoding of codes. And, this thesis investigates some key problems of QC-LDPC codes. The main works are summarized as follows:First, Some constructed approaches of LDPC codes are systematically summarized. A constructed method of QC-LDPC codes based on finite field is described in detail. And encoding and decoding methods of LDPC codes are also systematically summarized. Especially, the encoding algorithm for QC-LDPC codes is emphatically introduced. And, the Min-Sum algorithm(MSA) is also described in detail.Based on theoretical analysis above, combined with the hardware simulation, the FPGA implementation method of encoding and decoding for QC-LDPC codes are proposed, and all the modules in the FPGA design and the hardware simulation results are also introduced. The encoding scheme is based on the generator matrix of the quasi-cyclic structure, Normalized Min-Sum algorithm(MMSA) algorithm is used in the decoding scheme.