Delay Fault Detection Function In The DFT Implementation

With the rapid development of integrated circuits, circuit design method has reached a very high level of abstraction, so that the problem faced by more and more tests, tests in numerous art boundary scan test more and more people’s attention. This paper describes the background and now the whole boundary scan, the current research and current development trend. Be based on the existing circuit test methods are summarized from the overall presentation of the existing test methods, and for each test method is now a brief introduction and summary of their advantages and disadvantages and give the test. The paper focused on the current boundary scan test technology are introduced emphatically introduced its basic structure and circuit model is applicable from basic IEEE 1149.1 test method. Along the history, the current boundary scan test technology has been developed to the IEEE 1500 standard, this paper focuses on IEEE 1500 standard boundary-scan test method.Topics of this article is based on IEEE1500 standard test, test the integrity of the IEEE 1500 standard introduction and overview of its scalable core test architecture, and studied architecture in this clock pulse filter, give two clock domains the clock pulse filter model, its models and theories developed simulation clock pulse filter structure. On the IEEE 1500 standard test we made certain improvements to the input and output registers certain improvements allowed by switching multiplexer signal instead of the triggering event for the purpose of updating the conversion signal. Secondly, the clock control circuit must improve, given the delay test clock controller model. For IEEE 1500 core TAP controller 16 FSM certain improvement and state machine simulation improved the outcome. Delay-fault test sequence is given certain instructions and simulation results. Finally, summing up the contents of the foregoing proposed overall improvement of infrastructure, and the test sequence added to the TAP controller controls the simulation results obtained, given the delay time to failure is calculated based on the simulation results, according to the results of previous studies given area the relationship between the fault and the delay circuit.