Hardware Implementation Of Image Recognition Algorithm In Visual Prosthesis Based On VGG Model

Visual impairment seriously affects the daily life of individuals,and the study of artificial visual prostheses brings hope to the visual recovery of blind people.However,due to limitations in electrode materials,manufacturing,and implantation,the number of electrodes that can be implanted in patients is relatively small,resulting in lower image resolution.Therefore,the image processing research of visual prosthesis is one of the core of visual prosthesis research.The application of convolutional neural network on visual prosthesis can help visual prosthesis work better.This paper studies the application of convolutional neural network classification and recognition algorithm design on visual prosthesis and the implementation of convolutional neural network hardware accelerator.In this paper,we use the VGG model as the basis and combine the input image as a low-resolution image in the visual prosthesis application to crop the VGG model and improve the network to ensure that the classification accuracy meets the needs of the visual prosthesis.It has faster prediction speed and smaller hardware cost.Firstly,for the proportion of the fully connected layer parameters of the VGG model in the entire network,and the calculation is very intensive,the global average pooling layer is used to replace the fully connected layer,which reduces the parameters in the network;then,to further compress the network parameters,this paper The channel compression of the VGG model reduces the model parameters by 34.61%again,and a lightweight network suitable for visual prosthesis is obtained.The improved VGG model is trained and tested on the CIFAR-10 data set based on the TensorFlow deep learning framework.The test results show that the improved VGG model obtained 91.66%accuracy.Compared with the neural network model with similar depth,the improved VGG model is 0.47%higher in accuracy than the model in reference[38],and has similar classification accuracy.This paper completes the design of the hardware accelerator for the improved VGG model.By further analyzing the characteristics of the improved VGG model,the hardware accelerator architecture for multi-layer convolution parallel computing is realized.The design scheme of each functional module is elaborated in detail,the design of the accelerator is completed using verilog language,and the modelsim function simulation verification of each functional module is carried out.Then,the function of the accelerato r was verified on the ZCU-102 development board,and its correctness was analyzed using an online logic analyzer.The performance of the designed hardware accelerator is evaluated.The evaluation results show that the hardware accelerator designed in this paper can reach the peak processing speed of 208FPS at a clock frequency of 150MHz,which is 13.87 times the CPU processing speed.