| Starting from the birth of computer, bus technology went through a relatively long development process. Because of the disadvantage in speed, the serial bus has not been accepted by the computer industry in the early years of the development process. With the announcement of the IEEE1394 standard, the industry’s attention have been attracted by its low latency, point-to-point special transmission mode, support to transfer mode of isochronous data etc. With the standard of IEEE1394 serial bus have been gradually improved and perfected, it also has excellent performance of high-speed transmission and stability in bandwidth. For this reason, it is no longer just as an important technology of interface that interconnects the video transmission equipment in multimedia in initial period, it now has been applied to the avionics system which requires high qualities in real-time transmission and high reliability, and even more widely used in digital media devices and network’s interconnection.In this paper, we focus on the interface module between physical layer(PHY) and link layer(Link), it is an integral part of physical layer in IEEE1394. It provides an interface to the interaction and access of data between the logic control of physical layer and the logic control of link layer. The module is mainly responsible for decoding the serial requests started by link layer, synchronizing data in packets comes from link layer, processing format of packets, processing and forwarding data in packets received by physical layer and indicating some real-time status of interface such as Reset, Disable, Initialization and Link On. According to the different external input, link layer has different work patterns. The work patterns of interface is also divided into two kinds: Alpha mode and Beta mode. These two modes has the same basic function, expect on some aspects such as the clock pulse in work, the transmission mode in state and speed, the cascade method, etc. This paper analyzes and studies the performance characteristics of PHY-Link interface modules in two modes respectively.Based on the understanding and analysis on the protocol of IEEE1394b-2002 standard for a serial bus, this paper briefly describes the structure and basic features of IEEE1394 protocol firstly, and makes a detailed description on functions and relations of each module in physical layer of IEEE1394.Then it focus on analyzing howPHY-Link interface works and proposing an design on the interface module, which result in completing the IP core design of IEEE1394 PHY-Link interface. This design not only realized the basic functions in traditional designs of PHY-Link interface ruled by 1394,but also disposed the special cases in transmission and the change in state of interface properly.After that, according to the standard of function and verification, we briefly describes the process of building virtual verification platform and detailed Simulation Verification on the functions of interface IP core which uses NC-Verilog for simulation. Finally, we described the FPGA verification on digital parts of this design. In order to achieve this verification, a link layer model has been designed. And through the analysis test by host, the results are observed and judged whether they meet the requirements.According to the results of virtual and FPGA platform, the design of PHY-Link interface IP core can meet the requirements in functions and timing ruled by IEEE1394 protocol. It entirely meets the requirement on aspects of transmission between link layer and physical layer, and the status of interface. It can be seen that the design of PHY-Link interface can achieve the desired goal. |
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