Design And Verification Of Link Interface For IEEE1394Physical Layer

IEEE1394is a high-performance serial bus standard, it defines a hardwarehierarchy of three layers: the transaction layer, the link layer and the physical layer.Physical layer acts as a bridge between link layer and serial bus, and it realizes theconnection between a1394device and cable. To satisfy the high-speed half-duplexdata transfer with link layer for Alpha and Beta operation modes, physical layer needslink interface which should support both operation modes.The design and verification of link interface for physical layer were mainlystudied in this dissertation. Firstly, the development of IEEE1394bus was presented,as well as its technical features. Secondly, a brief introduction was given to thestandards, with emphasis on the functions of physical layer, and with reference to theproject Development of Physical Layer for IEEE1394Serial Bus, the structure ofphysical layer and connections between link interface and each module were described.Thirdly, according to the IEEE1394a-2000and IEEE1394b-2002standards, thefunctions and timings of link interface were analyzed, module division and designschemes of each sub-module were established. Finally, in order to guarantee thevalidity and reliability of the design, the verification platform was built, relevant testcases were developed according to functions of link interface, and direct verificationwas performed with NC-Verilog simulation software.The verification results indicate that, the design of link interface meets therequirements of IEEE1394standards in functions and timings, and it realizes aconnection with link in both operation modes.