| With the rapid progress of computer technology, people have been developing more and more requirements for the speed and reliability of data transfer. IEEE 1394 serial bus has put Point-to-Point data transfer into reality as a kind of open technology standard. And it has been widely applied in video and audio areas, including digital imaging, multimedia, mass storage and so on. Moreover, it shows wide application prospects in peripheral equipments of computer and internetworking. This kind of serial bus has numerous advantages, including supports for plug-and-play and two basic data transfer services, extensible feature, easy and convenient operation, low cost, etc. All of these have made IEEE 1394 the top choice for high-speed device interfaces.This design aims to develop an applicable IEEE 1394 link layer IP core to meet the CMOS image sensor developed by lab independently. It can be embedded in the CMOS image sensor when required. Or the IP core can be taped out separately in order to be embedded in other special processors. These will significantly lower the production cost and design complexity of related equipments.This dissertation has described the structure of the IEEE 1394 serial bus, the working theory of the link layer, and the architecture plus function of the link core. And it proposes a RTL (Register Transfer Level) design for IEEE 1394 link core based on Cyclone serial FPGA(Field Programmable Gate Array) of Altera and the link layer chip (TSB12LV01B) from TI. Besides, this dissertation gives details on logical design, functional simulation and timing verification mainly on the transfer of asynchronous data packages. The generated timing simulation wave accords with the specification of this model standard, and it realized the function of transferring various asynchronous data packages. This possesses both referential and practical values for the fundamental preparations on the upcoming research on IEEE 1394 link layer IP core with its own controllers. |
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