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System Of Data Collecting Aud Processing For Capacitive Screen Based On FPGA

Posted on:2016-12-02Degree:MasterType:Thesis
Country:ChinaCandidate:Y ZhaiFull Text:PDF
GTID:2308330482453309Subject:Software engineering
Abstract/Summary:PDF Full Text Request
At Present, Digital signal acquisition and processing are widely used in every electronics field. There are variety methods for the achievement of hardware. With the fast development of FPGA in recent years, the advantage of data collection used by FPGA reflects gradually.FPGA is super ultra high-speed, large-scale and programmable logic device that has been used extensively in recent years, because it has a lot of merits for example that high speed, high integrated level, programmable in system etc. It has brought the automation of the digital system design. It has shortened single digital system design cycle, improved the flexibility and dependability of design.This design is a practical application of the signal acquisition and processing system based on FPGA. The application task is to collect the V-I of any point on the capacitive screen of "capacitive touch screen parameter measurement systems" and dispose the data to obtain processing results. In order to make the measurement operation can issue instructions from the host computer and the host computer can measure the data back, so to support the MCU write special registers and data storage area.This paper studies the design of the three systems : First, FPGA gates any point on the matrix which has 256*256 aisles through a combination of FPGA and multi-channel analog switches. Second, the section of acquisition and processing includes the signal acquisition module and the filtration module and the algorithm processing module. The signal acquisition module controls A/D converter to convert the analog signal that output from the points of matrix into a digital signal. After that, the module put the collected data into the FIFO buffer. The filtration module filters the data of the FIFO by using the smoothing filtration and put the data into the RAM of the FPGA. The algorithm processing module disposes the data of the RAM by the method of successive minus and put the result into the MCU. The connection between the three modules is so close. The design meets 80 MHz sampling rate and 16 bits accuracy. Third, the design makes MCU write and read special registers and RAM of the FPGA by using the agreement of MCU.
Keywords/Search Tags:FPGA, Data collection, Low-pass filtering, FSMC interface
PDF Full Text Request
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