Design Of CPU Based On MIPS Architecture And Implementation Of SoC

CPU is the core of electronic information products, is the most technologically intensive semiconductor industry, the most strategic value products, but also a symbol of national technical strength. The work of CPU design is carried through to possess the momentous academic value and realistic value. Large number of domestic and international literature suggests that some scholars have successfully implemented CPU on FPGA. However, Most of CPUs have not test the performance rigorously, and scholars didn’t achieve a whole system on chip, so their CPU can’t be used practically.This design implements a 32 bits CPU of MIPS architecture, and a complete SoC system with the CPU as the master core. The main work is as followed:in the aspect of CPU implementation, PC calculation, reading of instruction cache, access of branch history table, hit detection of instruction cache, replacement selection of instruction cache, way selection of instruction cache, access of instruction bus, update of instruction cache, branch prediction, prediction of return address, reading of general registers, instruction decoding, handling of data hazard, arithmetic operation, multiply and divide operation, branch operation, reading of data cache, hit detecting of data cache, replacement selection of data cache, way selection of data cache, access of data bus, update of data cache, access of privilege registers, system timer, handling of exception return, writing back to general registers and other functions are realized. In the aspect of SoC implementation, this thesis implements AMBA bus matrix, AHB arbiter, AHB decoder, AHB2APB bridge, FLASH control IP core, UART control IP core, VGA control IP core, and ports a open source SDRAM control IP core from OpenCores to this system. As a result, a completed SoC system is created.In the aspect of testing CPU and SoC, each module is simulated by VCS software and debug by Verdi software respectively. And result show that the system work correctly and the scheme of system is realiable. The maximum operating frequency of SoC can work up to 60.27MHz after synthesizing on Cyclone IV FPGA and analyzing the static timing, reaching the design target. This thesis uses Dhrystone and CoreMark benchmark testing programs to test the fix point performance of this CPU, the fix point scores are 1.40 DMIPS/MHz and 2.35 CoreMarks/MHz. At last, this thesis ports ucos ⅱ embedded operation system to this SoC system to further verify the correctness.