A Study Of Customized Processor IP Core Design Using WIPER

This project is from Core Research for Evolutional Science and Technology. It is a research point of key technology research of IP core design. And it is about high performance IP core design and reuse of IP core, the project is coming from it.IP(Intellectual Property) core is a hardware description language program with specific circuit functions, as for the bit width of a processor IP, 4bit,8bit,16bit and 32bit IP are developed. But, present processor IP core can only execute programs of a fixed bit width. Customers usually have to prepare different IP cores to execute programs of different bit width. Therefore, IP core which can execute programs of different bit width can be executed after IP customization is needed for the convenient use of IP and the economic consideration. For this purpose, this paper proposes a Customized Processor IP core. The design mainly has three parts: 1) Instruction Set design:on the base of MIPS32 instructions that the MIPS32 IP provides, I add some MIPS16 instruction to the source code of the MIPS32 and define them. 2) Register File design:In the design of register file of MIPS16, implementation method of RAM on chip is adopted. The registers of MIPS32 mainly adopt original logic element implementation method. 3) Handshake Protocol design: WIPER is adopted as the design tools to choose the bit width, through the design of Handshake Protocol, we establish a protocol between WIPER and the source code of the Customized Processor IP core.This IP core mainly has three features, that is 1)wide applicability 2)higher performance and suitability for user requirements and 3)low power consumption. And on the base of it, we delete the multiply instruction, and get a new IP core with higher performance.