Research And Design Of MIPS4Kc IP Core And Related SOC

IC is stepping into the era of SOC with the increasing of chip scale. An inevitable trend ofIC design is designing based on IP. IP cores with outstanding versatility and flexibility can beapplied in various embedded-systems specified by different application.This dissertation implements a soft IP core compatible with MIPS4Kc CPU and builds aSOC that contains memory, UART and other peripherals around the core. Low-level driversand applications are developed and verified on Altera’s development board. Researchingconsists of both HW part and SW part.In HW part, the core is divided into modules and implemented by Verilog based onanalysis of MIPS4Kc architecture. The pipeline has five stages. Stalls caused by relativity areavoided by bypass between stages. Multiplier is improved by using Wallace-tree structure.Instruction and data cache are both4KB. The bus interface unit is compatible with Wishboneprotocol. The SOC consists of memory, UART, LED and segment display module.In SW part, boot-loader code is written to initial the system after reset. Drivers for UARTand other peripherals are developed to use HW resources on the DSP Development Board. Atop application program which can perform character re-display is used to verify the system.Since the core is compatible with MIPS4Kc, codes are compiled by GCC.The project is verified at module level and hazard case under Modelsim SE andsynthesized and timing-simulated under Quartus II and Modelsim SE. Verification iscompleted on the hardware under Quartus II. The results of verification and reports ofsynthesis indicate that the design is compatible with MIPS4Kc and has excellent performing.It can run at70MHz without too much resource cost.This project builds an elementary SOC with essential modules in developing and debug.The CPU core is fully compatible with MIPS4Kc, it makes software developing convenienceby compiling code with GCC. In a word, it makes foundation for later SOC developing forspecified requirements.