Design And Implementation Of A DMA Host-controller To Support Mul-transmission Mode

High performance and low power are two lasting targets for the development of Digital Signal Processors(DSPs). The performance of the DSP is lmited by the data exchange speed. Since the Direct Memory Access(DMA) controller is the core component of the data exchange, the DSP puts very high performance requirement on the DMA controller. This makes the design of the DMA controller face several challenges. Thus, this thesis delves into the design of the DMA host-controller to enhance the data transmission efficiencies.YHFT-X DSP is a high-performance 64-bit DSP processor independently developed by the NUDT. To enhance the overall performance of the DSP, we conduct several optimizations for the DMA controller. The DMA controller supports 20 logic channels, thus, it can efficiently handle many internal or external events. The DMA controller leverages a dual-port RAM structure to storing the transmission parameters, and it allows the core and the DMA controller to simulatenously read or write the parameter RAM. The DMA controller utilizes a round-robin arbiter to choose the appropriate logic channel to start, and this round-robin arbiter efficiently reduces the queuing time for the waiting logic channels. The DMA controller uses a very wide data bus to provide high transmission bandwidth. Finally, the DMA controller provides four transmission modes, and each transmission mode is specialized for some transmission situations. Thus, the DMA controller can efficiently meet with the requirements of several different data transmission situations.The four transmission modes include traditional point to point transmission, subsection transposition, broadcast transposition and matrix transposition. Subsection transposition is used for multi-core synergetic data transport. It is only one DMA is busy in the core, and put the data from thestorage out of the core(DDR) to one or more cores, according to some rules. Then DDR will inprove the access speed, and reduce the ring blocking under this transmission mode. Broadcast transposition is a special transmission mode as to Subsection Transposition, and put the data from thestorage out of the core to all the cores. Matrix transposition is a special type of point to point transmission mode, that digital signal processing core application, such as FFT, requires extensive matrix transpose operations. The programmer only configure once, the DMA will do point-to-point data transposition and matrix transposition. And the design utilizes a Ping-pong mechanism to improve the efficiency of matrix transpose with out-of-order data return.After the DMA host-module with mul-transmission mode logic design, we make the function verification and logic synthesis in the multi-core module. And make the timing and area optimized. The design is realized by the way based on standard cell, adopting the 40- nanometer-artwork standard cell library. Through many iterations of synthesisâ†'analysisâ†'coding, the DMA controller can content timing restraint under 450 ps. Finally we reach the design goal.