Design And FPGA Verification Of One-Shot Face Recognition Algorithm Based On Deep Transfer Learning

Thanks to the rapid development of the hardware capabilities and the technologies of collecting and storing data,deep learning has now become the most popular machine learning method.Collecting and tagging data,however,is laborious and time consuming.Thus,fully utilizing few labeled data to get a generalized model has become a valuable topic.One shot face recognition which uses merely one face sample per person to train a deep model is a representative task.As it minimizes the amount of data required by the deep learning-based face recognition algorithms,it has significant practical significances and broad application prospects.This thesis designed a one-shot face recognition algorithm based on deep transfer learning and verified it on FPGA.In terms of the design of the algorithm,a brand-new algorithm named Alternate Feature Recalibration Adversarial Transfer Training was proposed which introduces the feature recalibration blocks to typical one-shot deep learning networks and alternately optimizes the feature extraction part and the feature recalibration part of the network with different training batch sizes.Alternate Feature Recalibration Adversarial Transfer Training solved the problem that the extracted features in typical adversarial transfer training will not cluster.In terms of FPGA verification,the network was implemented via High Level Synthesis,and by developing a multithreaded Linux application,the forward propagation of the network has successfully run on the Xilinx Zynq-7100 FPGA via the collaborative work of the processing system part and the programmable logic part.The network design in this thesis only contains 10.66 M parameters and 1.89 G MACs.It also obtained a brand-new state-of-the-art top-1 recognition accuracy rate of 84.62% on the one-shot face recognition dataset WSC-Face via Alternate Feature Recalibration Adversarial Transfer Training.In FPGA verification,the network reached a forward inference speed of 10.13 FPS with a PL clock frequency of 142 MHz.The one-shot face recognition algorithm and the rapid FPGA verification scheme this thesis proposed have certain reference values for the mobile implementations of the highaccuracy real-time one-shot face recognition systems.