The Design Of 1024-ponts Float Pipelined FFT IP Core

At present, with the rapid development in the field of radar, communication, image processing, etc, there’s a greater demand for timeliness, high-speed performance, accuracy and high-capacity operation of signal processing techniques. As the most basic transform of digital signal processing, Fast Fourier Transform(FFT) is the core of digital signal processing, How to design a high-speed and high-accuracy FFT IP core has become the focus of research of domestic and foreign researchers.This paper used the radix 22 SDF structure to complete the 1024 point 32-bit floating point FFT IP core design. Firstly using Matlab to verify the feasibility of the structure, then using Verilog Hardware Description Language to design the butterfly operation unit, and the floating point arithmetic unit design. After the verification succeeded, Design the top level module to achieve the design of the pipelined FFT IP core. The co-simulation results of Model Sim and Matlab show that the IP FFT core’s function is correct. It is synthesized by using SMIC 0.18mm CMOS technology and the speed is expected to reach 243 MHz, and the cost of time of completing one time 1024 ponits 32 floating-point operations is only 5.375 μsTo further evaluate the IP Core, The XC7Z020CLG484 chip of the new programmable Xilinx ZYNQ series was adopted to build data transmission system based on Ethernet, Realized the commnication between FPGA development board and PC. PC program using socket network programming function to realize, Use visual studio to complete the server program design. The client program design is based on the Lw IP lightweight TCP/IP protocol stack, after processed the received data, The results show the function of FFT IP core is correctly. Meanwhile the comparison and error analysis of the Processing results, The analysis results show that the IP FFT core can meet the design requirements in the design precision.