| Phase-locked loop(PLL) frequency synthesizer is an essential block of RF receivers in satellite navigation systems. The frequency synthesizer affects the performance of the receivers. A fraction-N frequency synthesizer for satellite navigation RF receiver is presented in this paper.Two drawbacks of traditional PLL frequency synthesizer are analyzed: On the one hand, the loop bandwidth which determines the synthesizer’s lock time, phase noise and spur, will lose optimal state due to the influence of process, temperature and voltage(PVT) or the change of output frequency. On the other hand, the AFC process, which will cost additional time to find out the optimal sub-band tuning curve before the loop locking process, meets with a conflict between AFC time and AFC resolution.In this paper, the tuning gain KVCO is hold and the current of charge pump is forced to matches the divider ratio to keep the loop bandwidth at the optimal state. The existed constant KVCO technique is limited by process in high frequency and lower KVCO application. A switched capacitor array and switched varactor array topology is proposed, so that a low constant KVCO can be achieved at high frequency field. Then the PFD/CP, ΔΣ modulator and the reconfigurable divider is analyzed and designed to depress the phase noise of frequency synthesizer.Aiming at contradiction between AFC time and AFC resolution, a fast and accurate AFC technique, which is based on counter and phase-detector, is proposed. By adopting a counter to count the VCO frequency and a phase detector to detect the VCO phase at the start and stop count signals, the precision is improved without degrading the AFC time.Finally, the frequency synthesizer is designed in TSMC 0.18μm CMOS. The tuning gain KVCO vary less than 10% over the whole output frequency which range from 2790 MHz to 3480 MHz. The AFC cost only 0.611μs for 4-bit switched capacitor array. The frequency synthesizer exhibits phase noise of-87.72dBc/Hz@100KHz. |
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