Research On The Design Technology Of Cryptographic Processing Unit Operator Based On Double Logic

The cryptographic operation unit is the basis for the design of specialized instruction cryptographic processors and coarse-grained reconfigurable cryptographic arrays.In this paper,we study reconfigurable nonlinear Boolean function operation units and general cryptographic processing unit design techniques,starting from Boolean function design implementation.The main work and innovation points of the paper are as follows:The characteristics of cryptographic processing unit coding link and operation bit width of group cipher and sequence cipher are analyzed and extracted,focusing on the cryptographic characteristics of the nonlinear Boolean function of sequence cipher,and the hardware implementation schemes of mode addition,mode multiplication,finite field multiplication,and nonlinear Boolean function are analyzed and studied to provide theoretical support and model reference for the research of this paper.In response to the problems of poor support for the calculation of higher product terms of Boolean functions and large resource consumption in existing studies,a design scheme of reconfigurable nonlinear Boolean function arithmetic unit based on And-Inverter Cone(AIC)is proposed,a nonlinear Boolean function arithmetic unit for coarse-grained reconfigurable logic arrays is designed,and the data distribution network circuit is improved.It has also been physically implemented and experimentally verified based on a 40 nm CMOS process,and the results show a 67.8% reduction in area and a 39.2% reduction in delay compared to a cell with the same functionality.The Reed-Muller(RM)logic expression form of Boolean functions and the NPN equivalence class problem are investigated,and a four-variable RM-type general logic cell circuit architecture with only nine input ports is proposed to combine the characteristics of sequential cryptographic Boolean functions,improve the input and output settings of the cell,and design two high-performance nonlinear Boolean function computation cells for RISC processor applications.By coordinating with multiple instructions,arbitrary nonlinear Boolean functions can be implemented,and most of them can be operated within 3 instructions,and the maximum need is 9 instructions.Physical implementation and experimental verification were performed in CMOS 40 nm process,and the unit area was optimized by 85.5% and 91%,and the delay was optimized by 25.9% and 43.7%,respectively,compared with the design unit in Chapter 3 of this paper.The circuit structure of cryptographic arithmetic units such as modular-addition,modular-multiplication,finite-domain multiplication,and nonlinear Boolean functions is investigated,and a generic double-logic operator unit(Reconfigurable And-Xor-Nand,RAXN)that supports the form of and-inverter and and-xor logical expressions,which can be reconfigured to implement the common three-variables logical functions in a variety of cryptographic algorithms,is proposed and the circuit structure is given.A Reconfigurable Hybrid Granularity Multifunctional Cryptographic Arithmetic Unit(RHMCA)has been designed using RAXN to address the problem of low resource utilization due to the separate design of cryptographic arithmetic units.It can be reconstructed to implement 32 bit addition,8 bit multiplication,GF(28)finite field multiplication,S-box table lookup operations,and nonlinear Boolean function operations.Finally,physical implementation and experimental validation were performed based on CMOS 40 nm process,and the results show that the proposed multifunctional unit optimizes the best case of delay by 1.27 ns and reduces the area delay product by a maximum of 44.8% compared with the conventional implementation.