Power And Area Optimization Of Mixed Polarity Reed-Muller Logic Circuits

Power and area optimization of Reed-Muller (RM) logic circuits is an important aspect of logic synthesis for integrated circuits. Previously, power and area optimization of RM logic circuits focused on fixed polarity Reed-Muller (FPRM) logic. In fact, mixed polarity Reed-Muller (MPRM) logic circuits contain FPRM logic. Therefore, the optimization performance of MPRM logic circuits is better, also the optimal space is bigger and the conplexity is harder than FPRM logic circuits.For an n-variable logic function, 3~n mixed-polarities are possible. These MPRM expressions deriving from the same logic function with different mixed-polarities vary in size, so that the power and area performances of MPRM logic circuits using these espressions are different. Consequently, the main contents of this thesis are as follow:1) mixed-polarity conversions: according to the research of the docomposed rules of ordered kronecker functional decision diagrams, the conversion techniques of tabular methods, the operation skills of AND/XOR and the desscribailities of multi-output logic functions, four novel mixed-polarity conversion algorithms are proposed;2) low-power mapping for MPRM logic circuits: according to the dynamic power consumptions of CMOS circuits, the transmission characteristics of signal probability for two-input AND/XOR circuits and the decompositions of switching activity minimization, the fast power mapping algorithms for both static and dynamic MPRM logic circuits are proposed;3) area optimization for MPRM logic circuits: based on the research of the mapping methods and circuit constructions for Reed-Muller programmable logic array, an area estimation model is established, and combining the tabular conversion algorithms the best polarity of the minimum area of both mid-small and large scale MPRM logic circuits are found by enumeration method and simulate annealing genetic algorithm respectively;4) power optimization for dynamic MPRM logic circuits: based on the analysis of the low-power decompositions of AND/XOR circuits, the power and area estimation models are established, and combining mixed-polarity conversion algorithms and low-power decompositions enumeration method and genetic algorithm are applied in power optimization for both mid-small and large scale dynamic MPRM logic circuits respectively;5) power optimization for static MPRM logic circuits: based on an overall consideration of switching activity and load capacitance at nodes, the power and area of MPRM logic circuits is estimated by using gates from a given library, and combining mixed-polarity conversion algorithms and low power decompositions the best low-power mixed-polarities of both mid-small and large scale static MPRM logic circuits are found by enumeration method and immune genetic algorithm respectively.The proposed algorithms have been coded in C, and our experiments over several MCNC and ISCAS benchmark circuits show that compared to traditional two-level Boolean logic circuits and FPRM logic circuits, our algorithms achieved better optimize performance in terms of power dissipation and area.