Research On Temperature And Error Rate-Awared 3D IC Test And DVFS

Through-Silicon Vias provide high-density, low-latency, and low-power vertical interconnects through a thinned-down wafer substrate, thereby enabling the creation of 3D-Stacked ICs.3D (Three-Dimensional) Memory Stacking has become one of the most effective ways to solve insufficient internal memory capacity of the chip and bandwidth limitation in 2D ICs (Integrated Circuits), which based on its advantage on high memory capacity in unit area and low latency in vertical direction. However,3D ICs high power consumption density which caused by its high integration density increases the temperature of internal chip, and it may lead to Hot Spot. Obviously, high heat reduces the chip’s reliability, add the error rate of the chip, and limited 3D chips functions.Point to the high error rate leaded by temperature, there is one passive way which is to test the super scale of the integrate circuit. This thesis describes the new 3D stacking chips test procedure base on TSV, the challenges of Pre-Bond Test and reliability and testing challenge of TSVs postbond. Including KGD and KGD wafer-level test and burn-in, DFT skill, prebond testability, economics of test, reliability and testing problem of TSVs postbond, including problems that are unique to 3D integration, and summarizes early research results in this area.Another way is during the design of the chip, the designer will take the temperature and high error rate in the consideration. The thesis proposed a TERA-DVFS (Temperature and Error Rate-Aware Dynamic Voltage and Frequency Scaling) targeted to the chips with 3D Stacked Caches. Experimental result indicates that TERA-DVFS can lower its power consumption and gains better performance under the 3D cache’s temperature and error rate constraint.