Research In The Performance Prediction Model Under Different Frequencies

With the development of integrated circuit technologies, the complexity of microprocessor architecture design is ever increasing. Promoting the performance is still the primary current, while stability and validity also become the most important designing concerns. Dynamic Voltage and Frequency Scaling is an effective and widely-used technology, which regulate the voltage and clock frequency of processor to some set points. Thus, its application need accurate prediction of performance under different frequencies, according to which, the energy could be optimizing distributed.This thesis studies in the microprocessor performance under different frequencies, based on the simulation on a trace-driven simulator smtsim. By splitting the processor total cycles into memory accessing time and perfectly executing time, the variable part during frequency changing could be more focusing. Furthermore, through interval-analysis, each level2cache miss event that leads to memory accessing could be investigated dedicatedly. The whole procedure of cache miss is explained through the discussion of the bottleneck which account for the stalling of processor. The variation of cache miss during frequency changing is also examined.Thereby, research looks into the effect of overlapping of miss-events in level2cache on the performance of processor. We found that during a unit time, the memory accessing of several cache miss overlapped together, it leads to the inaccurate estimation of memory time from the total amount of miss-events. Through detailed analyses, by combining the isolated cache misses and discriminating recorded cache misses that happened in a certain period, the total length of memory accessing time can be calculated accurately. So that the main source of clock-cycles variation during frequency changing is accounted.Furthermore, the amount of miss-events that happened in an overlapping period will related to the memory accessing time, because the transfer of their requesting data will be limited to the bandwidth and memory accessing request resolving frequency. If the overlapping extent exceeded some point, the memory accessing time will increase correspondingly. However, monitoring the detailed overlapping number of miss-events will be costly, so that we use a regression model to utilize the accounted miss-events to obtain the total memory accessing time; the coefficients in the model are trained with a group of benchmarks. Above all, the prediction model is established, and is validated with SPEC CPU2000suite. The results show that this prediction model can accurately predict the performance of processor under different clock frequencies, which could be used to regulate the clock frequency of processor to a minimum acceptable point.