Reserach And Implementation Of Downlink Baseband Processing In C-RAN Digital Front End System

In the era of mobile Internet, mobile communications operators face serious challenges. With the rapid growth of mobile user data traffic, the number of radio communication base stations has increased dramatically. With traditional base stations increases, the processing load surge, resulting in consumption of base stations and maintenance costs increase. Through optimizing the network structure, and introduces the hardware accelerated platforms to centralized processing station data, C-RAN greatly reduces the system bandwidth and save the cost of the base station construction.This paper discusses a study of C-RAN downlink baseband digital front-end system. First of all, compare the scheme between the time-frequency division and channel division from the angle of baseband module division, the result shows that the channel division scheme greatly improve system efficiency with flexible structure and easy to upgrade. Then on the basis of the channel division scheme, implement complex module Turbo encoding and Singular Value Composition(SVD) on the three hardware platforms, DSP, GPU, FPGA, through the throughput of the two modules, power consumption performance contrast, eventually determine the FPGA is more suitable for processing baseband module.When implementing downlink baseband module on FPGA, the design of each module contains the packet definition, hardware structure and workflow. As the system design, the timing of each module have been strictly planned, including the timing of physical layer processing and transmission delay of high-speed interfaces such as PCIe, CPRI, 10 GE etc. Since the whole system involves different platforms, the design system transmission mechanism is also crucial. In this paper, a transmission format consists of a packet header and a serial of valid data has been adopted. Packets of the respective channels generated by the OAI software, DMA read symbols with specified length through PCIe, and finally through the way of packet header matching, each packet transmitted by CPRI timing after the completion of the baseband processing. This approach effectively guarantees the correctness of each module.Finally, in this paper the entire system, including OAI software, baseband modules, and interfaces were tested. Test platform is composed of software and hardware. In order to ensure the completeness of the system, testing scheme divide into three stages that is module level, link level, and system level, through functional simulation and board-level testing, the processing delay of each symbol is 42.71 us satisfying the system requirements of 66.67 us. C-RAN digital front-end system using Altera DE4 board, the total resource consumption is up to 50% when processing 4 antennas with 20 MHz bandwidth.