Research And Desigen Of Low Phase Noise Frequency Source

In recent years, with the rapid development of wireless communications, the demand on its functional diversity and performance stability gradually increases. The higher demands focus on frequency source. As it is the heart of communication equipment. The frequency source’s parameters including output frequency, bandwidth, frequency conversion speed, phase noise and spurious suppression of frequency source are particularly outstanding, while the phase noise improvement of frequency source has great significance on the performance of communication equipment. The aim of this thesis is to make three frequency sources, analyze and discuss the low phase noise of frequency source, and then research and design a module which meets the requirements. This thesis main content as following:First of all, the history of frequency source and its domestic and international dynamic development were elaborated in this thesis, so were the technical indexes to evaluate the performance of frequency source; then the phase-locked loop synthesis technology and direct digital synthesis technology were elaborated, which are two kinds of mainstream frequency synthesis technologies. We have made the corresponding analysis of the phase noise of frequency source; finally, analysis and summary were made regarding the variety of common synthetic scheme before design and production.In this thesis, single and low frequency output of three frequency sources are designed based on digital phase locked loop frequency synthesis technology, where the phase noise of the output signal is the core of the design. In order to get the output signal with low noise, a series of methods have been taken including selecting high performance crystal oscillator and low noise PLL chip, trying to control the power ripple. As for the control of chips, based on the datasheet the chips were designed to work in the best condition so as to realize the best working condition of the whole module and to control the phase noise degradation.Parameters of loop filter were determined through the simulation software and registers, and using VHDL language to control programmable chip realizing that the registers are controlled. The final layout and wiring of this design were completed via Protel software, FR-4 board is used for fabricating PCB board and the circuit were debugged and tested. The test results show that the phase noise of two clock frequency sources with 81.84 MHz clock can precede the design’s requirement of-105dBc/Hz@10kHz and the third phase noise of local oscillator frequency source reaches-95dBc/Hz@10kHz, which also meets the design requirements...