The VLIW Vector Processor Design For Mobile Telecom Baseband Algorithm

For the past few years, the evolution of mobile communication technology has been improving with each passing day. These new high technologies provide a powerful warranty for the coming of 4G or 5G era. However, with the better service the hi-tech bring to us, the heavier pressure may impose on the related processor. Furthermore, the mobile communication area will continue be exposed to the coexistence of multiple communication standards for a long time in the future, while it’s becoming harder and harder to find a new banlance between low power and high performance and programming flexibility by the communication processors we used today. Therefore, to solve the problems we mentioned above, this thesis researches and designs a new kind of application specific instruction processor(ASIP), combined with the Network on Chip(NoC) simultaneously, we built out a CoMP baseband communication system which orient to the 4G mobile communication standards.This thesis faces to the computation-intensive process which belongs to IMT-Advanced(4G) baseband processing, such as the CoMP precoding, channel estimation and equalization, FFT operation etc. By analyzing the features of these baseband algorithms in depth, we design a VLIW vector processor which contains double parallel characteristic, i.e, data level parallelism and the instruction level parallelism. In terms of the design of the VLIW vector processor’s architecture, we adopted a modified Harvard architecture. In respect of the instruction set, we designed a 5 stages pipeline by using the classical RISC instruction of MIPS for reference. At the same time, we designed several other application specific instructions according to the characteristic of the baseband algorithm to accelerate the implement of it. Besides, since the vector processor is verificated in a communication system based on NoC infrastructure, we designed several application specific instruction coprocessors to interconnect with NoC network to support the processing concurrency and the real-time requirement.At the last part of this thesis, we verify and test the VLIW vector processor and its coprocessors in a LTE base station platform which is composed of Xilinx Kintex7 serie FPGA. Besides the RTL level modeling and simulating by EDA tools, we also set up a practical CoMP scenario. Through the demonstration result, we can prove that the VLIW vector processor can execute the baseband signals processing of mobile communication system particularly well. Meanwell, the results of the demonstration show the VLIW vector processor’s three main superiorities: high speed of calculation, high data throughput rate and high performance of operating.