The Principle, Design And Performance Of Ultra High Speed Stochastic Turbo Decoder

Turbo code is the standard channel coding scheme for 3G and beyond 3G mobile systems. As the network specifications evolves, the baseband must support much high channel throughput. Thus, the high speed and low complexity decoding scheme is required for the mobile systems, especially for the user end. Due to the complexity and the properties of decoding scheme of Turbo codes, the increscent of decoding speed is the bottleneck for the system realization. In traditional methods, the high speed decoder can be achieved by module parallel schemes, but the system efficiency of power and area is limited. To solve this issue, a novel full parallel decoding method based on stochastic computation is proposed. Unlike conventional computation which uses weighted binary digits to represent numbers, stochastic computation uses random bit stream. To develop and verify this algorithm we carry out the following works.Max-log-MAP, the sub-optimal scheme for Turdo decoding algorithms, is studied,and some potential issues are found when stochastic computation is applied in. To solve these issues, some critical parameters are limited in specific range.After that the basic stochastic computation units for max-log-MAP algorithm are designed and their performance are analyzed. It is found that the decoding performances is indicated by the critical parameters of these units. By using simulation the optimal values of these parameters are found. From the performance analysis it is confirmed that the proposed method only has 0.1dB performance lose compared to ideal decoding algorithm.Then a fully parallel stochastic computation architecture is designed with hardware descriptive language. From the cross-checking between hardware simulation data and algorithm simulation data it is confirmed that the proposed design is correct and feasible.At last the proposed scheme is simulated in 130 nm CMOS technique. The result shows the proposed design can achieve at least 600 Mbps decoding speed with 100 MHz clock. If advanced technique is applied, the proposed design can easily reach up to 1Gbps speed. Compared to current industrial decoder, the proposed scheme achieves more 50%speed and hardware improvement.