HSPA-based Parallel Design Of Turbo Code Interface

In order to meet the growing demand for high-speed data services, the third Generation Partnership Project proposed High Speed Packet Access technical standards specifications, which includes HSDPA and HSUPA. High-speed information transmission puts forward new demands on the Turbo encoding and decoding technology. Turbo codes has been proposed since 1993, with its low SNR in the high performance, has been the most widely used,3G system also used the code as one of the channel coding schemes. Conventional Turbo encoder in order to get high-speed encoding, often at the expense of the cost of hardware resources, resulting in increased cost and not conducive to integration; the traditional Turbo decoder decoding algorithm itself which has a larger delay and throughput small shortcomings. According to the above-mentioned shortcomings of this thesis which based on the traditional program, a new parallel Turbo encoding and decoding technology proposed.In this paper, parallel Turbo encoder design using a single RAM parallel coding structure. Using the 32bit bit-width when the encoded data, each taken from the RAM in a 32bit data is encoded, the interleaving being suspended from one clock cycle, computing interwoven address, and in accordance with interleave address the data RAM to read out the first eight states sub-encoder, the second son of eight state encoder of the three operating joint implementation, the parallel output system bits, first parity bit, the second parity bits of data, thereby eliminating the conventional Turbo encoder is waiting under the interleave address generation idle time when the mixed data, while this paper the use of the coding sequence of calculations to optimize the s, in the prime number p can take maximum steps to reduce the 2048 calculation, so as to achieve the purpose of improving coding rate; the use of a single RAM to reduce the chip area of purpose.Parallel Turbo Encoder Decoder code block will be divided into overlapping blocks of 4 yards, so that four parallel sub-code block decoder decoding, eliminating the traditional serial Turbo decoder required to receive a full finished block and then decoding the data, but also forward and backward state metric calculations are based on when the data block, decoding delay larger shortcomings; and the use of four pipeline structure, the throughput increased four-fold. Turbo codec designed by Matlab simulation tests to verify the encoder in the HSUPA uplink, using 16x chip rate (61.44MHz),32bit-bit wide RAM conditions, to exercise maximum encode time block coding is less than 0.35ms; the decoder in the use of four parallel pipeline structure, and add redundant bits to 16 or 32, when the excellent performance curve.