A Fully Parallel Decoding Architecture Of Turbo Code And Its VLSI Implementation

For provide the multimedia service which needs to transmit mass data,the third generation mobile telecommunication must be able to transmit data at a high speed on the band limited channel.As the transmission media is a wireless channel which is unreliable and have uncertain noise,common error checking and correcting code cannot meet a higher service request.RS code connected with convolution code in series is always a common method to afford large quantity data transmission service during the passed years.Come along whit the invention of Turbo code,especially the profound research about it,Turbo code have been specified to be the important part of the standard channel coding scheme of WCDMA,CDMA2000 and TD-SCDMA in IMT-2000.In this dissertation we first study the coding and decoding algorithm of Turbo code,then simple analyze some algorithms usually be used to decoding the Turbo code and compare their calculation complexity.Have done this,refer to the detail request of 3GPP coding scheme,we improve the Constant_MAX_Log_MAX decoding algorithm by using a SW-WT technology and design a fully parallel decoding architecture.Based on the Matlab simulation result of the architecture,we study the VLSI design of a decodoer which use this architecture and under 3GPP standard decoding scheme.The whole design process we use VerilogHDL as the hardware description language,use 0.18um standard cells library for military use as the implementation method.During design the decoder,we analyze the algorithm's detail operating pattern both on time and memory space,and design a new SISO decoding module for our decoding architecture,which need less recursive calculating module while have the same scale register file compared to common SISO docoding modules.Then we use a "bottom-up" method simulate the decoder's function,emulate the decoding performance;and use a "top-down" method synthesize the decoder.At last we use 0.18 um standard cells library do the decoder's placement and route,analyze the design's area,power consumption etc.Improve and redesign some standard cells and IO cells to improve the decoder's reliability and performance,so as to use it in some special domain such as tactic broadcasting station used by single soldier.By taking care of the system parameter specification,functional module partition, memory optimization and parallel calculating,the decoder's decoding latency is shortened notably without the cost of operating frequency;by improve and redesign some standard cells and IO cells,the decoder's reliability and performance is improved; the VLSI implementation of the fully parallel decoding architecture is accomplished in the end.