The Research Of High Density Assembled Digital T/R Component

Since modern battlefield electromagnetic environment is becoming increasingly complex,the Digital Array Radar has become very popular in research areas of phased array radar technology for a lot of reason. By using digital beamforming technology, the Digital Array Radar can flexibly control beam direction and simultaneously send and receive multi-beam, which increase the ability to detect and track multiple targets. Meanwhile the Digital Array Radar has acquired multi-functional and strong anti-jamming capability by using the way of adaptive software to obtain zeros for signal receiving and processing. As the key component for a fully digital radar transceiver channel, the digital TR component has greater advantage over the traditional analog one because of its internal digital system architecture in the aspect of reliability, real-time control, the quality and complexity of transmitted signal and amplitude phase coherence of quadrature demodulation.The trend of miniaturizing the physical volume of Digital Array Radar promote high-density assembly technology began to be used for digital TR components. The Multi-chip Module technology(MCM) based on LTCC provide an effective way to realize a highly integrated digital TR components. The MCM based on LTCC has good high-frequency characteristics and thermal properties, and its characteristics which passive components can be buried inside the LTCC board could help to achieve a higher level of integration.This paper mainly focuses on the design of the digital part of the TR components circuit and high-density assembly structure. The system uses the Stratix II series FPGA as the core for signal control and data processing. DDRII act as data cache and the optical interface complete the high-speed data transmission between TR and radar signal processor connected in the later stage. High-performance complex radar waveforms is generated real-timely in the transmit channel by using a dedicated DDS chip solutions. AD chip and FPGA form the digital IF receiver architecture to preprocess the echo data by DDC in the receive channel. As for system integration, hardware circuits are divided into 4 sub-modules, and the devices are distributed on 4 LTCC substrates according to the principle of balanced power consumption, functional similarity, and miniaturized interconnection between LTCC boards. While routing wires on the LTCC board, some rules need to be followed such as protocol of electrical signals as well as the requirements for plate-making process, taking into account the impact on signal integrity. After the layout design of the sub-module substrates is completed, 2D_MCM is obtained by welding the device. Inside the annular separator, metallized through holes work for vertical interconnection between the substrates, forming the final 3D packaging stacked structure. In the final of the article, functional validation has been executed on the circuit design of the various sub-modules, and the debugging results illustrate the correctness of the hardware solution.