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13.56MHZ Electronic Tag Chip Analog Front-end Design

Posted on:2015-05-18Degree:MasterType:Thesis
Country:ChinaCandidate:P WangFull Text:PDF
GTID:2308330473952773Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
RFID technology plays a core role in the internet of things, the state has been very concerned about the development of RFID technology. RFID tag as a new automatic identification technology, compared to other automatic identification technologies such as bar codes, magnetic cards, having intelligence, capacity. RFID has been widely used in the transportation, logistics and other fields.In the RFID frequency, 13.56 MHz becomes the most widely used RFID band system for its recognition distance, low-cost market. At 13.56 MHz RFID tag chip, because the tag work in passive situations, requiring the entire chip operates at low power. The analog front end of the tag generate the power signal, clock signal, data signal, reset signal by receiving the electromagnetic wave signal. So the design of analog front end circuit plays an important role in the electronic tag.This paper will design the analog front end system of the 13.56 MHz RFID tag chip which meets the ISO/IEC15693 standard by being based on in-depth study of the electronic tag. First, the paper divide the entire analog front-end system to four module which are power management, modulation and demodulation, clock extraction and reset circuit and then determine the appropriate indicators, optimize the design for each module circuit. Such as the overvoltage protection circuit of power management module which ensure the tag antenna circuit can not exceed the maximum voltage by bringing the resistor divider. The Voltage reference circuit of power management module gets a high power supply rejection voltage reference circuit by using self-biased op amp. Electronic tag system which is designed in this paper achieve low power consumption and high reliability.The analog front end circuit of electronic tag has been already implemented with GSMC 018 process, using the spectre to simulation and designing layout by using Virtuoso. the chip conductes post-simulation with hspice by extracting the PEX parasitic. Finaly, the chip has been tested by using electronic equipment. Test results show that the design of the analog front-end circuit meet the system.
Keywords/Search Tags:electronic tag, power management, demodulation, ISO/IEC15693
PDF Full Text Request
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