Design An Rfid Chip Base On ISO/IEC 15693 Protocol

RFID(Radio Frequency Identification) technology,also known as radio frequency identification, RFID systems receive radio signals exchangedbetween the completion sent through space, so there is no need to read between the reader and the specific objective of establishing physical contact or optical class.Based on international standards ISO/IEC15693 protocol label system is mainly used for access control, logistics and identification applications such as distance recognition of this thesis work is to design a line with electronic tags that agreement. ISO/IEC15693 protocol defines the communication interface and communication data between electronic tag and reader specifications, operating frequency 13.56 Mhz, using this standard tag chip and reader read range of 0 to 1 m.Firstly, the paper gives a brief introduction to the background and development of radio frequency identification technology to, and then, Details of the international standards ISO/IEC15693 protocol,and designs a tag chip of digital part based on this protocol.The ASIC design uses a top-down design approach.the system has been divided for each module: decoding module, synchronization module, anti-collision module, EEPROMcontrol module, coding transmission module, coding control module, CRC checksummodule and string conversion modules and clock management module. Each module andTestbench are using Verilog-HDL hardware description language to achieve functionaldescription, and by using the tool ModelSim SE Plus 6.5 emulation. After the precedingtag chip design is complete RTL-level code, with Synopsys’ Design Compiler logic synthesis tools, and use integrated gate-level connections in the form of the resultingnetlist file into Encounter place and route, and extracted parasitic netlist files anddocuments after importing PT doing static timing analysis done with Formality formal verification, the match is correct with Nc-verilog simulation for each command successful.Various stages are designed to meet requirements in the agreement, and finally, the design on the GSMC 0.18μm CMOS process successfully taped, each command function test is successful, the simulation results are consistent with expectations.