Digital Circuit Design For Passive Tag Compatible To ISO/IEC 15693 Protocol

Radio frequency identification(RFID) is an automatic data collection and transmission technology that based on wireless communication. Using this technology, the reader reads identity of the target object via a chip attaching to it from a distance The RFID has advantages over traditional bar-code such as multi-object recognition, invisible identification and larger storage capacity. Even though cost has long been the obstacle to the RFID application, it now gains its opportunity again under the push by Internet of things(IoT). Thanks to the new technology, the management efficiency of many fields such as retail, logistics, transportation and food security is improved greatly.This paper is mainly about the design and implementation of the digital control system for passive tags compatible to the ISO/IEC 15693 protocol, which aims at the frequency of 13.56 MHz.The basic principles of RFID are introduced first, including the composition of RFID system, energy transimission and load modulation. Based on the study of the coding format, command format and operation of the tag, the whole digital system is divided into the flowing parts: decoder, CRC module, command storage module, read-write controller, encoder, clock divider and command processor. The function, I/O ports description, basic workflow, detail implementation and simulation results of each module are also given.The design is realized in Verilog HDL and simulated with ModelSim from Mentor Graphics Corp. After verified by Altera DE2-115 FPGA board, the design is synthesized with Design Compiler, performed static timing analysis(STA) with Prime Time and formal verification with Formality. The physical implementation is realized using Cadence APR tool SOC-Encounter. The design was successfully fabricated in 0.18?m COMS technology, achieving a chip size of 350 ?m×350 ?m. The chip was already tested and the chip performed as expected.