Design And Implement Ofmultichannel Parallel FFT And First Path Detector

With 7GHz of unlicensed bandwidth at 60 GHz, opportunities for short rangedmulti-Gb/s wireless communications open up for standards such as the IEEE 802.11.ad which applys both single-carrier and OFDM modulationmethods.The IEEE 802.11 ad standard supports SC PHY rates up to 1.76Gb/s.In order to eliminate the timingrecovery circuitry, the received samplesrates up to 3.52 Gb/s, originally up-sampled at least by the factor of two at the transmitter. In this paper, our modules including the symbol timing synchronization methodsand FFT/IFFT processorare presented.The transmission channel model will change at 60 GHz and a heavy dispersive and fading channel with deep/high peakspath elements is observed. For this kind of channel, the conventional method doesn’twork well due to the unexpected dispersive channel peak.The paper proposes a symboltiming synchronization method for extremely dispersive multi-path fading channels.With the complementary Golay sequence based preamble structure, the proposed synchronization scheme is designed to detect the preamble and the position of the first channel path.The architecture is designed as 8 ?-parallelism with data path and supports the single carrier(SC) transmissions of IEEE802.11.adstandards.The synchronization module is implemented as a part of a digital baseband receiver for IEEE 802.11.ad.In order to assess the effect of the algorithm, the experimental results find the BER reachs310?when the SNR is 8dB.The simulation also shows that the new algorithm can accurately find the first path underthe multipath channel,no matter the first path is the strongest one or not.A 256-piont FFT/IFFTprovideshigh throughput rate by applyingthe sixteen-data-path pipelined approach for wireless personal areanetwork application is also presented in this paper.A novelsimplification architecture to reduce the hardware cost in multiplication units of the multiple-path FFT approach is proposed.The CSD multiplier which has lower area than conventional complex multiplier is selected for our proposed architecture. Thearchitecture with a clock frequency 220 MHz clock processes a continuous flow of 16 samples in parallel,leading to a throughput of3.52Gb/s.The4 2 2Radix-2-2-2 reducessignificantly the number of rotators with respect to previousapproaches based on Radix-2. A multidata scaling scheme to reduce wordlengths while preserving thesignal-to-quantization-noise ratio is also presented. 256-point FFT implements every butterfly quantization strategy using a scaling factor of 1/2 without overflows in order of regularities and simplifications.TheSQNR performanceis 33.9 dB with 12-bit wordlength implementation.The function of the proposed FFT and symbol timing synchronization structure is verified by dynamic simulation. Then synthesis, place and route is completed with target device of Virtex 7 FPGA and the timing closure is reached, so the proposed modules is implemented on FPGA platform.