The Research Of SOPC System For Video Decoding Application

With the development of technology, video applications are getting more and more popular, and are changing the way we live, work and communicate. Unprocessed video usually has a large amount of data, which makes it inconvenient to store and transfer. Video compression, therefore, is needed to reduce the redundant information of video data. The H.264 is one of the most commonly used Video Compression Standards. It has the advantage of high compression rate and SNR, and thus suits low bit-rate video applications. There are many ways to implement a H.264 video codec, such as general-purpose processor based, ASIC based, DSP based and GPU based methods. In this thesis, the decoding of H.264 video was implemented by using the FPGA based SOPC. With the features of programmability and high flexibility, SOPC is quite suitable for prototyping of SOC design.Firstly, the H.264 video coding technique and the FPGA based SOPC development technology were introduced in this thesis. In order to implement the decoding of the low bit-rate H.264 video using the Xilinx FPGA, two kinds of SOPC design were introduced. One was based on software decoding, the other one was based on hardware decoding. In the software decoding based SOPC design, the decoding of the H.264 video was using the software decoding program, which was executed by the PowerPC processor. While in the hardware decoding based SOPC design, the decoding of the H.264 video was using the hardware circuit.In the software decoding based SOPC design, some Xilinx IP cores were introduced, such as PowerPC440, Crossbar, MPMC and tft controller. Using those IP cores, a hardware platform for embedded system, which was capable to run an operating system and support video output, was built under the XPS development enviorment. By porting the Linux OS and the open-source application MPlayer to the PowerPC based hardware platform, the SOPC system achieved the H.264 video decoding and displaying in a software method.In the hardware decoding based SOPC design, with the integration of a third-party H.264 hardware decoder IP core, the SOPC system was able to decode the H.264 video utilizing hardware, and to output the decoded data utilizing software. After verifying the the third-party IP core in Modelsim, the process of integration of user-defined IP core in XPS was discussed in details, including the implementation of PLB interface, creating the IP catalog and using the ChipScope to debug. The result of decoding test indicates that the system with the third-party decoding IP core supprots real-time H.264 baseline decoding of QCIF resoluton.In addition, the architecture of a hardware/software co-work H.264 decoder was presented, and the sub-module CAVLC was designed using Verilog. At last, The CAVLC design was confirmed correct through functional simulation in Modelsim.