Gbit TCP/IP Offload Engine Hardware Design And Implementation

Nowadays, with the high-definition television, video surveillance, intelligent vehicle control, aerospace and other high-tech remote control continuous development and progress, a lot of people on the real-time data transfer rates have become increasingly demanding, traditional pure software implementation of TCP/IP protocol to handle large amounts of data has started to show shortcomings, in order to achieve real-time high-speed data acquisition, this article propose a streamlined Gbit TCP/IP Offload Engine hardwired circuit design technique to achieve TCP/IP by FPGA pure hard-line approach agreement, the entire real-time data processing tasks to hardware TCP/IP protocol processing, experimental results analysis, design and implementation stage of this thesis hardware TCP/IP protocol to achieve data transfer rates an average of about 569.160 Mbps, showing that the technology not only network data transmission speed can be raised to the order of Gbps, but also as a result of reducing TCP/IP protocol processing of the CPU to unload the burden.Based on the TCP/IP protocol detailed theoretical analysis and specific studies, according to the characteristics of FPGA hardware, a streamlined Gbit can support high-speed data acquisition and transmission of TCP/IP hardware modules are designed and implemented. the last of all the major modules function board-level functional simulation and verification testing by multiple functional simulation and improve the final completion of the design TCP/IP protocol of each module will be designed to complete the hard-line protocol Bit file is loaded into Spartan-6 FPGA LX45 board development board conducted level verification debugging, use WireShark measured Gbit TCP/IP offload engine hard-line protocol can achieve data transfer rate can reach 569.160 Mbps, visible realization of this thesis Gbit TCP/IP offload engine hard-line protocol can significantly improve data transmission rate.This design Gbit TCP/IP Offload Engine module due to the hard line is now in the preliminary stages of development we do consider its application to low-end FPGA(such as the Spartan-6 or Spartan-3 Series development board) implemented on TCP/IP protocol processing tasks, in order to make low-end FPGA can achieve the high-speed data transmission processing functions, while also considering the rapid transmission generally applied to the camera image data and high-speed data acquisition; At a later stage, considering its IP core or made into an independent film production into separate streams hardware chips used in network servers to achieve server CPU offload engine function.