Research On Implementation Technology Of Bit Synchronization And Blind Equalization For QAM Signals

The most basic function of digital communication receivers is to receive correctly the transmitted data from the transmitter, and complete the corresponding inverse transform of the transmitter, including demodulation, decryption, decoding, and so on. At a final step, when an analog output, the source decoder attempts to reconstruct the original signal from the source. In digital communication system, the output of the demodulator must be sampled periodically, once per symbol interval, in order to recover the transmitted data. However, the band-limited channels may result in the ISI(inter-symbol interference) of the transmitted data and affect the sampling judgment. Therefore, the baseband algorithms, including the bit synchronization algorithms and equalization algorithms, become the core part at the receiver. The bit synchronization algorithms determine whether the bit timing is fast and accurate, and the equalization algorithms determine whether the data is transmitted correctlly transmission in the present of ISI. So the research of the bit synchronization and equalization of digital baseband transmission system is significant and important.In this thesis, a QAM signal baseband transmission system in the FDD(Frequency Division Duplexing) mode base on the FPGA platform is designed and implemented, where baseband transmission system has achieved the 80 Mbps data transmission speed. Furthermore, the focus of this hesis is put on the design and implementation of bit synchronization algorithm and blind equalization algorithm at receiver. The main works of this thesis are as follows:Firstly, the overall framework and the available basic techniques of the baseband communication systems is introduced, including convolutional encoding, scrambling, differential encoding, mapping, filtering, and so on.Secondly, the design and the implementation of the bit synchronization algorithm and the blind equalization algorithm at digital communication receivers are investigated.Aiming to bit synchronization, the basic principles of Gardner algorithm is first introduced, and the improved Gardner algorithm based on QAM signals is proposed. And then a simulink model bit synchronization loop is built and the appropriate parameter settings through the fixed-point simulation are determined. And finally the corresponding modules using verilog language are built and we complete the function testing and board-level validation. In blind equalization algorithm, an improved dual-mode Constant Modulus Algorithm(MCADAMA) is investigated. The design ideas and steps of the blind equalization algorithm are similar to bit synchronization module.Finally, after the implementation of the bit synchronization algorithm and the blind equalization algorithm, this thesis has tested the entire baseband transmission system based on FPGA platform. The test results show that the designing bit synchronization and blind equalization algorithm are feasible, and the receiving performance has achieved meets project requirements.