Research And FPGA Implementation Of Blind Synchronization Algorithm

In wireless communication system,the receiver needs to use synchronization parameters to demodulate the received signal and extract useful information.Synchronization algorithm is the key to obtain synchronization parameters.The performance of the algorithm directly determines the communication quality,especially in the non-cooperative communication scenario.The non-cooperative receiver uses blind synchronization algorithm to estimate synchronization parameters without any prior information,which is of great significance to the intelligence analysis of intercepted signals.The existing blind frame synchronization algorithms have low error tolerance,aiming at the problem this thesis proposes a blind frame synchronization algorithm based on first order cumulant and error elimination.The existing blind symbol synchronization algorithm have low noise resistance,aiming at this problem this thesis proposes a blind symbol synchronization algorithm based on twice wavelet transform.Otherwise,the blind frame synchronization algorithm and blind symbol synchronization algorithm are implemented on FPGA(Field Programmable Gate Array)to verify feasibility and performance of the two algorithms.The main contents of this thesis are as follows:1.This thesis studies the blind frame synchronization algorithm,proposes a blind frame synchronization algorithm based on first order cumulant and error elimination and deploys this algorithm to FPGA for actual test.Firstly,the algorithm constructs a matrix of the received sequence and analyzes the probability of the frame length of the matrix to obtain the estimated length of frame.Secondly,the starting point of the frame and the synchronization code are estimated based on the estimated length.Lastly,the precise synchronization code is obtained according to the autocorrelation characteristics.The algorithm maintains a high accuracy when the BER(Bit Error Rate)is less than 0.2 and has higher error tolerance than the blind frame synchronization algorithm based on small area detection and first order cumulant.In addition,the design input of FPGA is completed by Verilog,the behavior level simulation and comprehensive implementation of FPGA design are completed by Vivado 2019.1,the generated bit file is downloaded to zc706 development board for debugging.The actual test results show that the algorithm deployed on FPGA has feasibility and superior hardware acceleration effect.2.This thesis studies the blind symbol synchronization algorithm,puts forward a blind symbol synchronization algorithm based on twice wavelet transform.The algorithm is deployed on FPGA for practical test.The received signal is firstly transformed by second-order wavelet transform,and then the FFT(Fast Fourier Transform)is used to analyze the spectrum of the transform results,the symbol rate estimation is finally obtained by comparing the spectrum results of different transform scales.The algorithm can maintain more than 95%recognition rate when the SNR(Signal to Noise Ratio)is more than 3dB for MASK(Multiple Amplitude Shift Keying),MPSK(Multiple Phase Shift Keying),MFSK(Multiple Frequency Shift Keying)and MQAM(Multiple Quadrature Amplitude Modulation)modulated signals,compared with the existing algorithms it has better anti-noise performance.In addition,the algorithm is deployed on FPGA for practical test,and the results show that the algorithm has good practicability and FPGA hardware acceleration effect.