Research And Development On Digital Calibration Algorithm Of Time Interleaved ADC

With the rapid development of the integrated circuit industry and the widespread applications of digital technology in the fields of information processing, storage and transmission, as the bridge of the real world and digital world, ADCs are becoming a hot research topic of related institutions at home and abroad. However, limited by the quality of integrated circuit design and manufacturing technology, after a period of rapid growth, the poformance of single channel ADCs is coming to a bottleneck. In time-interleaved ADC, several ADCs work parallelly and output the converted data in sequence. This architecture, which multiples the conversion rate without increasing design difficulty, provides an efficient way to break through the bottleneck of ADC’s development.However, the poformance of time-interleaved ADCs is seriously affected by inter-channel mismatches, such as offset mismatch, gain mismatch and sample clock skew. Detailed analysis on the causes, impact and reflection on frequency spectrum of these inter-channel mismatches is presented in this paper. After analysis and comparison of existing error calibration methods of the mismatches, we proposed an adaptive digital background calibration method, based on the statistical characteristic of these three kinds of nonideal factors. With the feasibility of the algorithm verified by Simulink, we built and tested the calibration architecture by verilog HDL and accomplished the physical synthesis, layout design and optimization, logic and timing check and post-simulation by digital IC back-end EDA tools. The calibration architecture is easy to implement with samall hardware consumption, the effect of calibration is obvious, for a 12 bits 800 MHz TIADC, the SNR is improved by 36 dB and the ENOB is improved by 6 bits.