| Mixed-signal system has become increasingly common in all kinds of applications.It makes the demands for ADC system which has always working as the interfaceconnecting analog domain and digital domain become wider and higher. ADC hasbecome the bottleneck which restricting the system frequency in many integratedcircuits design. Therefore the design of high speed and high resolution ADC hascurrently become a research focus. Time interleaved ADC structure is a very effectivechoice for achieving high speed ADC. However, the inter channels offset mismatch,gain mismatch and timing skew has severely lowered the Signal-Noise-Ratio(SNR).To solve this problem, our research has been focused on the inter channelsmismatch in time-interleaved ADC system and the design of its calibration system.After in-depth analysis on the causes and results of these inter channels mismatch, wedesigned a inter channels offset and gain mismatch calibration scheme which combinedboth front-end and back-end calibration. We also built a Simulink model of thecalibration scheme so we can verify the function and performance. By simulation, weget the all the limiting parameters which guarantee the system performance meet thespecification. And the Simulink model we built has always been the theoretical modeland design reference for all the following ASIC designing work. Then we brieflyintroduced the structure of the calibration system and the function of all the submodules. Since most of the time-interleaved ADC calibration systems are used in highspeed ADC application, so we analyzed the bottleneck in the system which mightrestrict the working frequency, then introduced the principles of pipeline and circuitsinterleaved techniques which is essential and wildly used in high speed digital circuitsdesign and we also introduced its application in our system. At last, we brieflyintroduced the digital ASIC designing flow which starts from coding to simulation,verification and all the digital back-end design. |
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