Research And Design Of High Voltage RESURF-LDMOS

LDMOS as a lateral power device all of its electrodes locate at the surface, thuseasier to be integrated monolithically with other low voltage signal circuits throughinterconnects. Now it has been employing more and more widely in power integratedcircuits in view of such advantages as high breakdown voltage, large gain and lowdistortion, etc. The design quality and reliability of LDMOS determine theperformance of the whole circuit. Traditional design method of LDMOS mainlysurrounds the trade-off between breakdown voltage and specific on-resistance. Butthere exists the fact that LDMOS has to endue big current and high voltage and thenoperates in high temperature region. So the design of safe operation area (SOA) isabsolutely necessary. As a result, breakdown voltage, specific on-resistance and SOAshould be considered synthetically so as to obtain the best performance both of devicelevel and circuit level.Under these conditions, we simulated and analyzed the main structure parametersof LDMOS, such as field plate, drift region et al. with 2D simulation soft MEDICI.Meanwhile, we has researched LDMOS's safe operation area (SOA), modeled thebreakdown characteristics and high temperature characteristics, which all can be usedto optimize the design of LDMOS.In this dissertation, we retrospected the development of power devices firstly, andthen introduced several junction termination techniques like Field Plate (FP), FieldLimiting Ring (FLR), and Variation of Lateral Doping (VLD) etc., which are adoptedprevalently in practical LDMOS design. Considering for the different applicationfields, some concrete LDMOS structures are presented in conjunction with thecomparison of main performance parameters.As FP's design is prone to be overlooked and left out, we have researched singleFP comprehensively. The results show that the length, oxide height, surface corrodingdepth of silicon active area which fabricates by LOCOS technology exert greatinfluence on breakdown voltage, respectively. And then a new double FP LDMOS was proposed, whose breakdown voltage and on-resistance are higher than single FPLDMOS. Because of the far-reaching impact on breakdown voltage and on-resistance,the drift region is designed and simulated in detail. For LDMOS with RESURFtechnology, we can obtain perfect trade-off between breakdown voltage andon-resistance through adjusting such parameters as drift region junction depth, lengthand implanted dose.The modeling of breakdown characteristics is a hotspot and nodus of LDMOS.We gave the all-sided research of breakdown characteristics containing the breakdownmechanism, breakdown position and compact model with the help of some otherpublished work.We also researched the safe operation area of LDMOS with non-isothermalsimulation. SOA is such a synthetical parameter that it matters many factors. Thecorresponding solution is proposed to the two SOA categories, namely long term SOAand short term SOA. According to the high temperature effects, threshold voltage andon-resistance were analyzed, which show that threshold voltage reduces nearlylinearly and on-resistance increases with parabolic curve against device temperature'senhancement.At last, process of LDMOS is designed, which do not employ the traditionalepitaxy technology but fabricate on substrate directly. The proposed process flow canbe taped out in either HVCMOS technology or BCD technology. We simulated theprocess with process simulation soft Tsuprem4. Finally, the layout of single LDMOSis designed for following's tape-out work.