Packet Parsing System Design And Implementation Based On SOPC

The rapid development of network technology and the increasing network bandwidth bring great convenience to people, but also bring enormous pressure to network devices. Packet processing technology has become a key factor which restricts the development of network. Traditional software processing occupies processor resources and has low rate, meanwhile, the hardware approach is attracting more and more attention. Packet parsing as the core technology of network devices has important significance.At the same time, considering the complexity of network environment and the diversity of network protocols, how to test the packet parsing structure truly and effectively becomes a difficulty and reseach point.Firstly, two packet processing technologies which include packet classification and packet parsing for high speed network are researched in this thesis. Three kinds of classification algorithms suitable for hardware implementation are analysed, the algorithm based on TCAM has fastest rate. The principle of packet parsing is illustrated and a new parsing structure is proposed by studying the two existing parsing structure and summarizing the advantages and disadvantages in this thesis. The structure is designed with TCAM and pipeline has two characteristics of high speed and flexibility.In order to make real and realible function verification and reflect the workflow of the hardware parser, the packet parsing system is designed in this thesis. The system can communicate with the Ethernet and display the parsing results on PC. Firstly, the system requirement is analysed, as the same time the design scheme of the system is put forward. TSE IP core and 88E1111 PHY chip are used to set up the SOPC system to communicate with Ethernet. And serial port is used to transfer the parsing results.Then on the basis of the overall structure of packet parsing system, using the top-down design method, repectively, the submodules are designed and implemented.After completing the system design, it is necessary to test the system. The test platform is built by using the DE4 development board, the chip is EP4SGX230KF40C2. Xcap software is used as the excitation source and the test scheme is given based on the system requirements. The test results show that the system can send and receive the Ethernet packet accurately, can parse packets correctly and transfer the parsing results to PC. In the process of work, system has no parsing errors and missing packets. It can verify the parser reliable, has a good display effect and the hardware resource consumption is 36%, meets the project requirements.