Research And Design On Lateral High Voltage Power Devices In A Switching Mode Power Supply Chip

Lateral high-voltage power device becomes the preferred device in power management IC design when compared with vertical one for its easy integration with standard CMOS process. However, its higher resistance and larger layout area always challenge the designers. In this thesis, a device with Triple RESURF structure and multi floating field plate is proposed which owns high breakdown voltage, low sepcific on-resistance, low process complexity and good scalability.The multi floating field plate designed in the triple RESURF LDMOS is to improve the device breakdown voltage of the surface and avoid the high leakage current generated by the resistive field plate by appling an approximately linear potential distribution on the surface of the drift region. The isolated triple RESURF structure consists of p-type deep well connected with p-body near source region is used to not only effectively reduce the on-resistance, but also increase the scalability of the device. An optimized structure with the junction depth ratio 1: 2: 7 and the dopant concentration ratio 1: 0.598: 0.072 of HVNW, DPW and BNW in the drift region can be obtained through the anylitical model. An optimized LDMOS with 793 V off-state breakdown voltage and 128.5 m?.cm2 specific on-resistance can be obtained through the 2D simulation when each field plate length LFFP = 4 μm, substrate concentration Npsub=1×1014 cm-3, drift region implant dosage DHVNW=2.6×1012 cm-2, DDPW=3.0×1012 cm-2, DBNW=1.0×1012 cm-2 and drift region length Ldrift=70 μm. A 20% reduction of specific on-resistance is achevied by multi floating field plate as compared with normal field plate. Analytical and numerical results showed good consistency.A Triple RESURF JFET with high on-state breakdown voltage and high process compatibility with LDMOS is designed by the reduced length of the source region. An optimized JFET with 774 V off-state breakdown voltage, 600 V on-state breakdown voltage and 20 V to 25 V pinch-off voltage can be obtained through 2D simulation when the source width equals 9.6 μm and the DPW pitch of the gate region is 3.5 μm. Measured and simulated results showed good consistency.The art-of-state high-voltage startup circuit with the complex power device, using the JFET pinchoff voltage as the gate voltage of the LDMOS, is designed to reduce the static power consumption and delay time of the conventional high-voltage startup circuit with depletion type LDMOS and JFET. Meanwhile, less extra layout area and less interference between two devices can be gained by the isolated triple RESURF structure. An optimized high-voltage startup circuit consists of complex power device with 20 ms delay time which is 50% shorter than the conventional JFET under the same condition can be obtained through the 2D simulation when the source width equals 20 μm, the DPW pitch of the gate region is 3.5 μm, charging capacitor C1 is 1 μF and the target voltage is 12.1 V. Furthermore, the static power is 8.7 mW when the drain voltage is 700 V and the resistor R1 is 2 M?. Measured and simulated results showed good consistency.