Study On SOI RESURF Principle And Fabrication Of SOI LDMOS

With the development of IC (Integrated Circuit), many novel power devices have been investigated extensively and intensively. With the invention of MOS-controlled power device, the concept of PICs (Power Integrated Circuits) has been proposed. In order to improve reliability and reduce volume, PICs integrates power device and logical circuits on the single chip.The success of PICs is mainly depended on the isolation between high voltage device and low voltage circuits. Due to ideal dielectric isolation and simple process, SOI (Silicon-on-Insulator) technology became promising for PICs. Meanwhile, SOI CMOS with inherent advantages is another major technology for next-generation VLSI.As the fundament of SOI PICs, SOI power devices have been attracted more attention recently. In this dissertation, SOI RESURF (Reduced Surface Field) principle is studied systematically.First, based on the solution of Poison equation in drift region, the analytical models for the surface potential, electric field and breakdown voltage are developed. The relations between the potential, electric field and device parameters are investigated. It is reasonable to explain the U-shape of potential distribution and the saturation of the breakdown voltage. The analytical results coincide well with numerical simulations and experimental data.Second, SOI RESURF is physically explained by charge-sharing concept. It concluded that the coupling of charges in the lateral pn junction and vertical depletion improved the block capability of SOI RESURF structure. The X parameter could be used to characterize SOI RESURF principle. This model could also fit well with numerical simulations and experimental data.Third, a novel partial SOI LDMOS is proposed. Based on STI (Shallow Trench Isolation), this structure has a window beside the source to extract self-heating efficiently. Moreover, this window could prevent hole stacking in the channel and eliminate floating body, although there is no body contact in this structure.Based on these studies, SOI LDMOS is successfully fabricated on SIMOX wafer (Separation by Implantation of Oxygen). The device could sustain the off-state breakdown voltage of 50V and on-state breakdown voltage of 20V respectively, which is suitable to control the field emission of carbon nanotube.Finally, a simple method for calculating the stress current in accelerated test of time dependent dielectric breakdown (TDDB) of stacked dielectrics is presented. By replacing an energy barrier of arbitrary shape with a series of rectangular energy barriers and resolving rigorously the Schrodinger equation in each regions, interfaces and variations of electron effective masses in different dielectrics have been analyzed. Our calculations fit experimental data well. The method is applicable in this reliability study aimed at failure mechanism detection and prediction.