Research Of The SPIC Layout Design On ESD Performence

Smart power integrated circuits(SPIC)are the general term of the high voltage IC and power IC. In recent years, with the progress of microelectronics technology, SPIC develops rapidly and becomes a key interface circuit on mechatronics. SPIC also is the core technology in SOC. It includes information collection, processing and power control. It is the crucial technical which caused the second electronic revolution. As same as the ordinary IC, SPIC is also affected by ESD,therefore,researching to improve the performance of ESD has a significant implications. In the mainstream CMOS process, as ESD protection device applications, GGMOS is used extremely broad. However, process shrink makes high performance GGMOS device design more difficult. So it necessary that make a deep research to analyze the factors which affect the performance of GGMOS, the layout have a crucial effect in ESD performance. However, process manufacturers provide data for ESD device is not complete, to improve ESD performance, it is need for designer to study the ESD device performance and optimize the layout through the simulation software. In this paper, the impact of SPIC layout design on ESD performance of the GGMOS are described and analyzed. The process is 180 nm standard CMOS process, the voltage is 5V.Firstly, it is necessary to get a brief introduction of two types of software(Medici and Cadence Virtuoso) used in research. Medici is device simulation software and Cadence Virtuoso is the layout design software. Basic grammar rules and procedures of the Medici are being analyzed and introduction the Virtuoso verification methods. Describe four models in common application and give out a series of ESD protection structures from the view of I/O pin. The importance of on-chip ESD protection expound fully in GGMOS device. Secondly, using Medici simulate the curve of the GGMOS which is used as ESD protection device. In different working conditions, the current distribution, electric field distribution, holes distribution and temperature distribution are compared and a comprehensive analysis is implemented to analyze the impact factors which effect the ESD performance of the GGMOS, including the gate length, GBCS, GDCS and GSCS. A depth analysis theoretically is implement to get a answer that these factor change the GGMOS performance, optimize GGMOS design and get a optimization GGMOS design. This paper analyzes the impact of the main parameters on GGNMOS, but for GDPMOS also useful. Finally, according to GGMOS layout design rules, we come up with some impact factors which will get influence on ESD performance, including the impact of the structure of the active region, the ends of the contact structure, the contact hole layout, latch-up phenomenon and sources and drain division. Proposed optimization scheme and analysis of the reason of these optimization programs brought, and these programs are implemented one by one.This paper analysis ESD protection devices for 5V GGMOS and provide a reference for the design of the above device through simulation results and layout research in 180 nm process. It will help improve design efficiency, reduce design costs and design a high-performance ESD protection device. The study showed that it can effectively improve ESD performance of the device, get the effective protection for SPIC.